/* USER CODE BEGIN Header */
/**
  ******************************************************************************
  * @file    ramecc.c
  * @brief   This file provides code for the configuration
  *          of the RAMECC instances.
  ******************************************************************************
  * @attention
  *
  * Copyright (c) 2025 STMicroelectronics.
  * All rights reserved.
  *
  * This software is licensed under terms that can be found in the LICENSE file
  * in the root directory of this software component.
  * If no LICENSE file comes with this software, it is provided AS-IS.
  *
  ******************************************************************************
  */
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "ramecc.h"

/* USER CODE BEGIN 0 */

/* USER CODE END 0 */

RAMECC_HandleTypeDef hramecc1_m1;
RAMECC_HandleTypeDef hramecc1_m2;
RAMECC_HandleTypeDef hramecc1_m3;
RAMECC_HandleTypeDef hramecc1_m4;
RAMECC_HandleTypeDef hramecc1_m5;
RAMECC_HandleTypeDef hramecc2_m1;
RAMECC_HandleTypeDef hramecc2_m2;
RAMECC_HandleTypeDef hramecc2_m3;
RAMECC_HandleTypeDef hramecc2_m4;
RAMECC_HandleTypeDef hramecc2_m5;
RAMECC_HandleTypeDef hramecc3_m1;
RAMECC_HandleTypeDef hramecc3_m2;

/* RAMECC init function */
void MX_RAMECC_Init(void)
{

  /* USER CODE BEGIN RAMECC_Init 0 */

  /* USER CODE END RAMECC_Init 0 */

  /* USER CODE BEGIN RAMECC_Init 1 */

  /* USER CODE END RAMECC_Init 1 */

  /** Initialize RAMECC1 M1 : AXI SRAM
  */
  hramecc1_m1.Instance = RAMECC1_Monitor1;
  if (HAL_RAMECC_Init(&hramecc1_m1) != HAL_OK)
  {
    Error_Handler();
  }

  /** Initialize RAMECC1 M2 : ITCM-RAM
  */
  hramecc1_m2.Instance = RAMECC1_Monitor2;
  if (HAL_RAMECC_Init(&hramecc1_m2) != HAL_OK)
  {
    Error_Handler();
  }

  /** Initialize RAMECC1 M3 : D0TCM-RAM
  */
  hramecc1_m3.Instance = RAMECC1_Monitor3;
  if (HAL_RAMECC_Init(&hramecc1_m3) != HAL_OK)
  {
    Error_Handler();
  }

  /** Initialize RAMECC1 M4 : D1TCM-RAM
  */
  hramecc1_m4.Instance = RAMECC1_Monitor4;
  if (HAL_RAMECC_Init(&hramecc1_m4) != HAL_OK)
  {
    Error_Handler();
  }

  /** Initialize RAMECC1 M5 : ETM RAM
  */
  hramecc1_m5.Instance = RAMECC1_Monitor5;
  if (HAL_RAMECC_Init(&hramecc1_m5) != HAL_OK)
  {
    Error_Handler();
  }

  /** Initialize RAMECC2 M1 : SRAM1_0
  */
  hramecc2_m1.Instance = RAMECC2_Monitor1;
  if (HAL_RAMECC_Init(&hramecc2_m1) != HAL_OK)
  {
    Error_Handler();
  }

  /** Initialize RAMECC2 M2 SRAM1_1
  */
  hramecc2_m2.Instance = RAMECC2_Monitor2;
  if (HAL_RAMECC_Init(&hramecc2_m2) != HAL_OK)
  {
    Error_Handler();
  }

  /** Initialize RAMECC2 M3 : SRAM2_0
  */
  hramecc2_m3.Instance = RAMECC2_Monitor3;
  if (HAL_RAMECC_Init(&hramecc2_m3) != HAL_OK)
  {
    Error_Handler();
  }

  /** Initialize RAMECC2 M4 : SRAM2_1
  */
  hramecc2_m4.Instance = RAMECC2_Monitor4;
  if (HAL_RAMECC_Init(&hramecc2_m4) != HAL_OK)
  {
    Error_Handler();
  }

  /** Initialize RAMECC2 M5 : SRAM3
  */
  hramecc2_m5.Instance = RAMECC2_Monitor5;
  if (HAL_RAMECC_Init(&hramecc2_m5) != HAL_OK)
  {
    Error_Handler();
  }

  /** Initialize RAMECC3 M1 : SRAM4
  */
  hramecc3_m1.Instance = RAMECC3_Monitor1;
  if (HAL_RAMECC_Init(&hramecc3_m1) != HAL_OK)
  {
    Error_Handler();
  }

  /** Initialize RAMECC3 M2 : Backup RAM
  */
  hramecc3_m2.Instance = RAMECC3_Monitor2;
  if (HAL_RAMECC_Init(&hramecc3_m2) != HAL_OK)
  {
    Error_Handler();
  }
  /* USER CODE BEGIN RAMECC_Init 2 */

  /* USER CODE END RAMECC_Init 2 */

}

/* USER CODE BEGIN 1 */

/* USER CODE END 1 */

