/* USER CODE BEGIN Header */
/**
  ******************************************************************************
  * @file    stm32h7xx_it.c
  * @brief   Interrupt Service Routines.
  ******************************************************************************
  * @attention
  *
  * Copyright (c) 2025 STMicroelectronics.
  * All rights reserved.
  *
  * This software is licensed under terms that can be found in the LICENSE file
  * in the root directory of this software component.
  * If no LICENSE file comes with this software, it is provided AS-IS.
  *
  ******************************************************************************
  */
/* USER CODE END Header */

/* Includes ------------------------------------------------------------------*/
#include "main.h"
#include "stm32h7xx_it.h"
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
#include "stdio.h"
/* USER CODE END Includes */

/* Private typedef -----------------------------------------------------------*/
/* USER CODE BEGIN TD */

/* USER CODE END TD */

/* Private define ------------------------------------------------------------*/
/* USER CODE BEGIN PD */

/* USER CODE END PD */

/* Private macro -------------------------------------------------------------*/
/* USER CODE BEGIN PM */

/* USER CODE END PM */

/* Private variables ---------------------------------------------------------*/
/* USER CODE BEGIN PV */

/* USER CODE END PV */

/* Private function prototypes -----------------------------------------------*/
/* USER CODE BEGIN PFP */

/* USER CODE END PFP */

/* Private user code ---------------------------------------------------------*/
/* USER CODE BEGIN 0 */

/* USER CODE END 0 */

/* External variables --------------------------------------------------------*/
extern DMA_HandleTypeDef hdma_adc1;
extern DMA_HandleTypeDef hdma_adc3;
extern ADC_HandleTypeDef hadc1;
extern ETH_HandleTypeDef heth;
extern MDMA_HandleTypeDef hmdma_quadspi_fifo_th;
extern QSPI_HandleTypeDef hqspi;
extern RAMECC_HandleTypeDef hramecc1_m1;
extern RAMECC_HandleTypeDef hramecc1_m2;
extern RAMECC_HandleTypeDef hramecc1_m3;
extern RAMECC_HandleTypeDef hramecc1_m4;
extern RAMECC_HandleTypeDef hramecc1_m5;
extern RAMECC_HandleTypeDef hramecc2_m1;
extern RAMECC_HandleTypeDef hramecc2_m2;
extern RAMECC_HandleTypeDef hramecc2_m3;
extern RAMECC_HandleTypeDef hramecc2_m4;
extern RAMECC_HandleTypeDef hramecc2_m5;
extern RAMECC_HandleTypeDef hramecc3_m1;
extern RAMECC_HandleTypeDef hramecc3_m2;
extern PCD_HandleTypeDef hpcd_USB_OTG_FS;
extern HCD_HandleTypeDef hhcd_USB_OTG_HS;
extern TIM_HandleTypeDef htim6;

/* USER CODE BEGIN EV */
extern void IRQ_Enter(signed IRQn, const char* Description);
extern void IRQ_Exit(signed IRQn, const char* Description);
/* USER CODE END EV */

/******************************************************************************/
/*           Cortex Processor Interruption and Exception Handlers          */
/******************************************************************************/
/**
  * @brief This function handles Debug monitor.
  */
void DebugMon_Handler(void)
{
  /* USER CODE BEGIN DebugMonitor_IRQn 0 */

  /* USER CODE END DebugMonitor_IRQn 0 */
  /* USER CODE BEGIN DebugMonitor_IRQn 1 */

  /* USER CODE END DebugMonitor_IRQn 1 */
}

/******************************************************************************/
/* STM32H7xx Peripheral Interrupt Handlers                                    */
/* Add here the Interrupt Handlers for the used peripherals.                  */
/* For the available peripheral interrupt handler names,                      */
/* please refer to the startup file (startup_stm32h7xx.s).                    */
/******************************************************************************/

/**
  * @brief This function handles DMA1 stream0 global interrupt.
  */
void DMA1_Stream0_IRQHandler(void)
{
  /* USER CODE BEGIN DMA1_Stream0_IRQn 0 */
  IRQ_Enter(DMA1_Stream0_IRQn, "\r+DMA1");
  /* USER CODE END DMA1_Stream0_IRQn 0 */
  HAL_DMA_IRQHandler(&hdma_adc1);
  /* USER CODE BEGIN DMA1_Stream0_IRQn 1 */
  IRQ_Exit(DMA1_Stream0_IRQn, "\r-DMA1");
  /* USER CODE END DMA1_Stream0_IRQn 1 */
}

/**
  * @brief This function handles ADC1 and ADC2 global interrupts.
  */
void ADC_IRQHandler(void)
{
  /* USER CODE BEGIN ADC_IRQn 0 */
  IRQ_Enter(ADC_IRQn, "\r+ADC");
  /* USER CODE END ADC_IRQn 0 */
  HAL_ADC_IRQHandler(&hadc1);
  /* USER CODE BEGIN ADC_IRQn 1 */
  IRQ_Exit(ADC_IRQn, "\r-ADC");
  /* USER CODE END ADC_IRQn 1 */
}

/**
  * @brief This function handles TIM6 global interrupt, DAC1_CH1 and DAC1_CH2 underrun error interrupts.
  */
void TIM6_DAC_IRQHandler(void)
{
  /* USER CODE BEGIN TIM6_DAC_IRQn 0 */
  IRQ_Enter(TIM6_DAC_IRQn, "\r+TIM6");
  /* USER CODE END TIM6_DAC_IRQn 0 */
  HAL_TIM_IRQHandler(&htim6);
  /* USER CODE BEGIN TIM6_DAC_IRQn 1 */
  IRQ_Exit(TIM6_DAC_IRQn, "\r-TIM6");
  /* USER CODE END TIM6_DAC_IRQn 1 */
}

/**
  * @brief This function handles Ethernet global interrupt.
  */
void ETH_IRQHandler(void)
{
  /* USER CODE BEGIN ETH_IRQn 0 */
  IRQ_Enter(ETH_IRQn, "\r+ETH");
  /* USER CODE END ETH_IRQn 0 */
  HAL_ETH_IRQHandler(&heth);
  /* USER CODE BEGIN ETH_IRQn 1 */
  IRQ_Exit(ETH_IRQn, "\r-ETH");
  /* USER CODE END ETH_IRQn 1 */
}

/**
  * @brief This function handles USB OTG HS global interrupt.
  */
void OTG_HS_IRQHandler(void)
{
  /* USER CODE BEGIN OTG_HS_IRQn 0 */
  uint32_t ch_num;
  HCD_HandleTypeDef* hhcd = &hhcd_USB_OTG_HS;
  uint32_t USBx_BASE = (uint32_t) hhcd->Instance;

  IRQ_Enter(OTG_HS_IRQn, "\r+USB_HS");
  if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_SOF) && hhcd->Init.dma_enable == 0)
  {
    for (ch_num = 0; ch_num < hhcd->Init.Host_channels; ch_num++)
    {
      // workaround the interrupts flood issue: re-enable NAK interrupt
      USBx_HC(ch_num)->HCINTMSK |= USB_OTG_HCINT_NAK;
    }
  }
  /* USER CODE END OTG_HS_IRQn 0 */
  HAL_HCD_IRQHandler(&hhcd_USB_OTG_HS);
  /* USER CODE BEGIN OTG_HS_IRQn 1 */
  if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HCINT) && hhcd->Init.dma_enable == 0)
  {
    for (ch_num = 0; ch_num < hhcd->Init.Host_channels; ch_num++)
    {
      if (USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NAK)
      {
        if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL) || (hhcd->hc[ch_num].ep_type == EP_TYPE_BULK))
        {
          // workaround the interrupts flood issue: disable NAK interrupt
          USBx_HC(ch_num)->HCINTMSK &= ~USB_OTG_HCINT_NAK;
        }
      }
    }
  }
  IRQ_Exit(OTG_HS_IRQn, "\r-USB_HS");
  /* USER CODE END OTG_HS_IRQn 1 */
}

/**
  * @brief This function handles QUADSPI global interrupt.
  */
void QUADSPI_IRQHandler(void)
{
  /* USER CODE BEGIN QUADSPI_IRQn 0 */
  IRQ_Enter(QUADSPI_IRQn, "\r+QSPI");
  /* USER CODE END QUADSPI_IRQn 0 */
  HAL_QSPI_IRQHandler(&hqspi);
  /* USER CODE BEGIN QUADSPI_IRQn 1 */
  IRQ_Exit(QUADSPI_IRQn, "\r-QSPI");
  /* USER CODE END QUADSPI_IRQn 1 */
}

/**
  * @brief This function handles USB OTG FS global interrupt.
  */
void OTG_FS_IRQHandler(void)
{
  /* USER CODE BEGIN OTG_FS_IRQn 0 */
  IRQ_Enter(OTG_FS_IRQn, "\r+OTG_FS");
  /* USER CODE END OTG_FS_IRQn 0 */
  HAL_PCD_IRQHandler(&hpcd_USB_OTG_FS);
  /* USER CODE BEGIN OTG_FS_IRQn 1 */
  IRQ_Exit(OTG_FS_IRQn, "\r-OTG_FS");
  /* USER CODE END OTG_FS_IRQn 1 */
}

/**
  * @brief This function handles MDMA global interrupt.
  */
void MDMA_IRQHandler(void)
{
  /* USER CODE BEGIN MDMA_IRQn 0 */
  IRQ_Enter(MDMA_IRQn, "\r+MDMA");
  /* USER CODE END MDMA_IRQn 0 */
  HAL_MDMA_IRQHandler(&hmdma_quadspi_fifo_th);
  /* USER CODE BEGIN MDMA_IRQn 1 */
  IRQ_Exit(MDMA_IRQn, "\r-MDMA");
  /* USER CODE END MDMA_IRQn 1 */
}

/**
  * @brief This function handles BDMA channel0 global interrupt.
  */
void BDMA_Channel0_IRQHandler(void)
{
  /* USER CODE BEGIN BDMA_Channel0_IRQn 0 */
  IRQ_Enter(BDMA_Channel0_IRQn, "\r+BDMA");
  /* USER CODE END BDMA_Channel0_IRQn 0 */
  HAL_DMA_IRQHandler(&hdma_adc3);
  /* USER CODE BEGIN BDMA_Channel0_IRQn 1 */
  IRQ_Exit(BDMA_Channel0_IRQn, "\r-BDMA");
  /* USER CODE END BDMA_Channel0_IRQn 1 */
}

/**
  * @brief This function handles RAM ECC diagnostic global interrupt.
  */
void ECC_IRQHandler(void)
{
  /* USER CODE BEGIN ECC_IRQn 0 */

  /* USER CODE END ECC_IRQn 0 */
  HAL_RAMECC_IRQHandler(&hramecc1_m1);
  HAL_RAMECC_IRQHandler(&hramecc1_m2);
  HAL_RAMECC_IRQHandler(&hramecc1_m3);
  HAL_RAMECC_IRQHandler(&hramecc1_m4);
  HAL_RAMECC_IRQHandler(&hramecc1_m5);
  HAL_RAMECC_IRQHandler(&hramecc2_m1);
  HAL_RAMECC_IRQHandler(&hramecc2_m2);
  HAL_RAMECC_IRQHandler(&hramecc2_m3);
  HAL_RAMECC_IRQHandler(&hramecc2_m4);
  HAL_RAMECC_IRQHandler(&hramecc2_m5);
  HAL_RAMECC_IRQHandler(&hramecc3_m1);
  HAL_RAMECC_IRQHandler(&hramecc3_m2);
  /* USER CODE BEGIN ECC_IRQn 1 */

  /* USER CODE END ECC_IRQn 1 */
}

/* USER CODE BEGIN 1 */

/* USER CODE END 1 */
